1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-089891, filed Apr. 8, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, with the rapid progress in miniaturization and high density of semiconductor devices, it has been becoming more difficult to ensure sufficient manufacturing margin for manufacturing processes, and extremely high processing precision has been required for a photolithography process performed by an exposure apparatus, and the like. For example, regarding errors in alignment of a photomask with a pattern formed on a semiconductor wafer, errors in position control of a mask stage and a wafer stage, have been nonnegligible.
On the other hand, a manufacturing apparatus, which includes multiple wafer processors that are independently-controllable and perform wafer processes in parallel, has been developed to enhance the throughput of the manufacturing apparatus. However, multiple wafer processors have different occurrence tendencies of control errors. For this reason, it has been necessary to specify a wafer processor for each wafer to be processed in order to ensure high processing precision.
Japanese Patent Laid-Open Publication No. H11-162842 and No. H06-267809 disclose techniques of setting processing conditions and managing processing states for each wafer with use of wafer IDs (Identifications).
According to the technique disclosed in Japanese Patent Laid-Open Publication No. H11-162842, a processing condition for a first lithography process is stored with a wafer ID. Then, a wafer ID on a wafer is read upon a second lithography process. Then, the processing condition for the first lithography process is invoked to perform the second lithography process.
Japanese Patent Laid-Open Publication No. H06-267809 discloses a multi-chamber apparatus that includes multiple process chambers, wafer loader chambers, and wafer unloader chambers. Each chamber is provided with a wafer ID reader. Thus, setting of processing conditions and management of processing states are enabled.
According to the above two techniques, however, a pattern of the wafer ID is formed on a wafer. For this reason, if a film is formed on the pattern of the wafer ID, or the shape of the pattern of the wafer ID is changed by an etching process, errors in reading the wafer ID occur in some cases. Each time a reading error occurs, operation of the wafer processing apparatus stops, thereby lowering the operation rate of the wafer processing apparatus.
When the wafer processing apparatus includes multiple wafer processors, robot arms called a wafer loader supply, from a wafer carrier housing multiple wafers, the wafers to wafer processors. It is necessary to supply wafers to all the wafer processors, to perform wafer processes in parallel and to maintain high throughput. Regarding the above techniques using the wafer ID, however, there is occasionally a wafer processor to which no wafer is supplied since no wafer is specified with respect to the wafer processor. In this case, the wafer processor does not operate, thereby lowering the operation rate of the wafer processing apparatus. Further, the wafer loader reads the wafer ID for each wafer, and determines a wafer processor to which the wafer is supplied. For this reason, the wafer loader has to operate randomly, thereby increasing wasted motions. Accordingly, it becomes difficult to perform the optimal and smooth control of the wafer loader, thereby lowering the operation rate of the wafer processing apparatus.